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general description the max5948a/MAX5948B are hot-swap controllers that allow a circuit card to be safely hot plugged into a live backplane. the max5948a/MAX5948B operate from -20v to -80v and are well-suited for -48v power systems. the max5948a is pin- and function-compati- ble with both the lt1640al and lt1640l. the MAX5948B is pin- and function-compatible with both the lt1640ah and lt1640h. the max5948a/MAX5948B provide a controlled turn-on to circuit cards preventing glitches on the power-supply rail and damage to board connectors and components. the max5948a/MAX5948B provide undervoltage, over- voltage, and overcurrent protection. these devices ensure the input voltage is stable and within tolerance before applying power to the load. both the max5948a and MAX5948B protect a system against overcurrent and short-circuit conditions by turning off the external mosfet in the event of a fault condition. both devices feature an open-drain power-good status output, pwrgd for max5948a or pwrgd for MAX5948B, that can be used to enable downstream converters. the max5948a/MAX5948B are available in an 8-pin so package. both devices are specified for the extended -40? to +85? temperature range. applications central-office switching network switches/routers server line cards base-station line cards features ? allow safe board insertion and removal from a live -48v backplane ? pin- and function-compatible with lt1640al/lt1640l (max5948a) ? pin- and function-compatible with lt1640ah/lt1640h (MAX5948B) ? withstand -100v input transients with no external components ? operate from -20v to -80v ? programmable inrush and short-circuit current limits ? programmable overvoltage protection ? programmable undervoltage lockout ? power up into a shorted load ? power-good control output max5948a/MAX5948B -48v hot-swap controllers with external r sense ________________________________________________________________ maxim integrated products 1 gate sense v ee 1 2 8 7 v dd drain ov uv pwrgd (pwrgd) so top view 3 4 6 5 max5948a MAX5948B ( ) for MAX5948B. pin configuration ordering information 19-3473; rev 0; 10/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max5948aesa -40? to +85? 8 so MAX5948Besa -40? to +85? 8 so typical operating circuit appears at end of data sheet. selector guide part pwrgd polarity max5948aesa active low ( pwrgd ) MAX5948Besa active high (pwrgd)
max5948a/MAX5948B -48v hot-swap controllers with external r sense 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages are referenced to v ee , unless otherwise noted.) supply voltage (v dd - v ee ) .................................-0.3v to +100v pwrgd, pwrgd .................................................-0.3v to +100v drain (note 1)........................................................-2v to +100v sense ....................................................................-0.3v to +20v gate (internally clamped) .....................................-0.3v to +18v uv and ov..............................................................-0.3v to +60v current through sense ....................................................?0ma current into gate...........................................................?00ma current into any other pin................................................?0ma current into drain............................................-100ma to +20ma continuous power dissipation (t a = +70?) 8-pin so (derate 5.9mw/? above +70?)...................471mw operating temperature range ...........................-40? to +85? junction temperature .....................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v ee = 0v, v dd = 48v, t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted.) (notes 2, 3) parameter symbol conditions min typ max units power supplies operating input voltage range v dd 20 80 v supply current i dd uv = 3v, ov = v ee , sense = v ee 0.7 2 ma gate driver and clamping circuits gate pin pullup current i pu gate drive on, v gate = v ee -30 -45 -60 ? gate pin pulldown current i pd any fault condition, v gate = 2v 24 50 70 ma external gate drive ? v gate v gate - v ee , 20v v dd 80v 10 13.5 18 v gate to v ee clamp voltage v gsclmp v gate - v ee , current into gate = 30ma 15 16.4 18 v circuit breaker current-limit trip voltage v cb v cb = v sense - v ee 40 50 60 mv sense input bias current i sense v sense = 50mv 0 -0.03 -1 ? uv pin uv high threshold v uvh uv low to high transition 1.213 1.243 1.272 v uv low threshold v uvl uv high to low transition 1.198 1.223 1.247 v uv hysteresis v uvhy 20 mv uv input bias current i inuv v uv = v ee 0 -0.5 ? ov pin ov high threshold v ovh ov low to high transition 1.198 1.223 1.247 v ov low threshold v ovl ov high to low transition 1.165 1.203 1.232 v ov hysteresis v ovhy 20 mv ov input bias current i inov v ov = v ee 0 -0.5 ? pwrgd output signal referenced to drain drain input bias current i drain v drain = 48v 10 80 250 ? p ow er - g ood thr eshol d v pg v drain - v ee , high to low transition 1.1 1.4 2.0 v p ow er - g ood thr eshol d h yster esi s v pghy 0.4 v note 1: test condition per figure 1. drain current must be limited to the specified 100ma maximum.
max5948a/MAX5948B -48v hot-swap controllers with external r sense _______________________________________________________________________________________ 3 electrical characteristics (continued) (v ee = 0v, v dd = 48v, t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted.) (notes 2, 3) parameter symbol conditions min typ max units pwrgd, pwrgd output leakage i oh pwrgd (max5948a) = 80v, v drain = 48v, pwrgd (MAX5948B) = 80v, v drain = 0v 10 ? power-good output impedance (pwrgd to drain) r out pwrgd (MAX5948B) (v drain - v ee ) < v pg 500 x 10 3 m ? pwrgd output low voltage v ol v pwrgd - v ee; v drain - v ee < v pg , i out = 5ma (max5948a) 0.11 0.4 v pwrgd output low voltage v ol v pwrgd - v drain ; v drain = 5v, i out = 5ma (MAX5948B) 0.11 0.4 v ac parameters ov high to gate low t phlov figures 2, 3 0.5 ? uv low to gate low t phluv figures 2, 4 0.4 ? ov low to gate high t plhov figures 2, 3 3.3 ? uv high to gate high t plhvl figures 2, 4 3.4 ? sense high to gate low t phlsense figures 2, 5 2 3 4 ? max5948a, figures 2, 6 0.5 drain low to pwrgd low drain low to (pwrgd - drain) high t phlpg MAX5948B, figures 2, 6 0.5 ? max5948a, figures 2, 6 0.5 drain high to pwrgd high drain high to (pwrgd - drain) low t plhpg MAX5948B, figures 2, 6 0.5 ? note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to v ee , unless otherwise specified. note 3: limits are 100% tested at t a = +25? and +85?. limits at -40? are guaranteed by design. 2v 100ma max max5948 pwrgd/pwrgd ov uv v ee v dd drain gate test voltage sense figure 1. -2v drain voltage test circuit
max5948a/MAX5948B -48v hot-swap controllers with external r sense 4 _______________________________________________________________________________________ t ypical operating characteristics (v dd = 48v, v ee = 0v, t a = +25?, unless otherwise noted.) supply current vs. supply voltage max5948 toc01 supply voltage (v) supply current ( a) 80 90 60 40 20 70 50 30 10 100 200 300 400 500 600 700 800 900 0 0 100 supply current vs. temperature max5948 toc02 temperature ( c) supply current (ma) 75 50 25 0 -25 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -50 100 gate voltage vs. supply voltage max5948 toc03 supply voltage (v) gate voltage (v) 90 80 10 20 30 50 60 40 70 2 4 6 8 10 12 14 16 0 0 100 gate voltage vs. temperature max5948 toc04 temperature ( c) gate voltage (v) 75 50 25 0 -25 12.5 13.0 13.5 14.0 14.5 15.0 12.0 -50 100 circuit-breaker trip voltage vs. temperature max5948 toc05 temperature ( c) trip voltage (mv) 75 50 25 0 -25 49 50 51 52 53 54 55 48 -50 100 gate pullup current vs. temperature max5948 toc06 temperature ( c) gate pullup current ( a) 75 50 -25 0 25 41 42 43 44 45 46 47 48 40 -50 100 v gate = 0v
max5948a/MAX5948B -48v hot-swap controllers with external r sense _______________________________________________________________________________________ 5 v s r 5k ? v ov v uv v+ 5v v sense v drain 48v max5948a MAX5948B pwrgd/pwrgd ov uv v ee v dd drain gate sense figure 2. test circuit 1 t ypical operating characteristics (continued) (v dd = 48v, v ee = 0v, t a = +25?, unless otherwise noted.) gate pulldown current vs. temperature max5948 toc07 temperature ( c) gate pulldown current (ma) 75 50 25 0 -25 35 40 45 50 55 60 30 -50 100 v gate = 2v pwrgd output low voltage vs. temperature (max5948a) max5948 toc08 temperature ( c) pwrgd output low voltage (mv) 75 50 -25 0 25 5 10 15 20 25 30 35 40 0 -50 100 i out = 1ma 10,000 1000 100 10 1 -50 25 -25 0 50 75 100 pwrgd output impedance vs. temperature (MAX5948B) max5948 toc09 temperature ( c) output impedance (g ? )
max5948a/MAX5948B -48v hot-swap controllers with external r sense 6 _______________________________________________________________________________________ timing diagrams 1.223v ov t phlov 0v 2v 1v 1.203v 1v t plhov gate figure 3. ov to gate timing t phluv 1.223v 1v 1v 1.243v t plhuv uv 0v 2v gate figure 4. uv to gate timing 50mv 1v 100mv gate sense v ee t phlsense figure 5. sense to gate timing drain pwrgd v pwrgd - v drain = 0v 1.8v v ee drain 1v v ee 1.8v 0v t plhpg 1v 1.4v t phlpg 1v 1.4v t phlpg 1v pwrgd drain figure 6. drain to pwrgd /pwrgd timing
max5948a/MAX5948B -48v hot-swap controllers with external r sense _______________________________________________________________________________________ 7 detailed description the max5948a/MAX5948B are integrated hot-swap controllers for -48v power systems. they allow circuit boards to be safely hot plugged into a live backplane without causing a glitch on the power-supply rail. when circuit boards are inserted into a live backplane, the bypass capacitors at the input of the board? power module or switching power supply can draw large inrush currents as they charge. the inrush currents can cause glitches on the system power-supply rail and damage components on the board. the max5948a/MAX5948B provide a controlled turn-on to circuit cards preventing glitches on the power-sup- ply rail and damage to board connectors and compo- nents. both the max5948a and MAX5948B provide undervoltage, overvoltage, and overcurrent protection. the max5948a/MAX5948B ensure the input voltage is stable and within tolerance before applying power to the load. board insertion figure 6a shows a typical hot-swap circuit for -48v sys- tems. when the circuit board first makes contact with the backplane, the drain to gate capacitance (c gd ) of q1 pulls up the gate voltage to roughly i(v ee x c gd ) / (c gd + c gs )i. the max5948_ features an internal dynamic clamp between gate and v ee to keep the gate-to-source voltage of q1 low during hot insertion, preventing q1 from passing an uncontrolled current to the load. for most applications, the internal clamp between gate and v ee of the max5948a/MAX5948B eliminates the need for an external gate-to-source capacitor. resistor r3 limits the current into the clamp circuitry during card insertion. pin description pin max5948a MAX5948B name function 1 pwrgd power-good signal output. pwrgd is an active-low open-drain status output referenced to v ee . pwrgd is low when v drain - v ee v pg , indicating a power-good condition. pwrgd is open drain otherwise. ? pwrgd power-good signal output. pwrgd is an active-high open-drain status output referenced to drain. pwrgd is in a high-impedance state when v drain - v ee v pg , indicating a power-good condition. pwrgd is pulled low to drain otherwise. 22ov input pin for overvoltage detection. ov is referenced to v ee . when ov is pulled above v ovh voltage, the gate pin is immediately pulled low. the gate pin remains low until the ov pin voltage reduces to v ovl . 33uv input pin for undervoltage detection. uv is referenced to v ee . when uv is pulled above v uvh voltage, the gate is enabled. when uv is pulled below v uvl , gate is pulled low. uv is also used to reset the circuit breaker after a fault condition. to reset the circuit breaker, pull uv below v uvl . 44v ee device negative power-supply input. connect to the negative power-supply rail. 55 sense current-sense voltage input. connect to an external sense resistor and the external mosfet source. the voltage drop across the external sense resistor is monitored to detect overcurrent or short-circuit fault conditions. connect sense to v ee to disable the circuit- breaker feature. 66 gate gate-drive output. connect to gate of the external n-channel mosfet. 77 drain output-voltage sense input. connect to the output-voltage node (drain of external n-channel mosfet). 88v dd positive power-supply rail input. this is the power ground in the negative-supply voltage system. connect to the most positive potential of the power-supply inputs.
max5948a/MAX5948B -48v hot-swap controllers with external r sense 8 _______________________________________________________________________________________ power-supply ramping the max5948a/MAX5948B can reside either on the backplane or the removable circuit board (figure 6a). power is delivered to the load by placing an external n-channel mosfet pass transistor in the power- supply path. after the circuit board is inserted into the backplane and the supply voltage at v ee is stable and within the under- voltage and overvoltage tolerance, the max5948a/ MAX5948B turn on q1. the max5948a/MAX5948B grad- ually turn on the external mosfet by charging the gate of q1 with a 45? current source. capacitor c2 provides a feedback signal to accurately limit the inrush current. the inrush current can be calculated: i inrush = (i pu x c l ) / c2 where c l is the total load capacitance, c3 + c4, and i pu is the max5948_ gate pullup current. figure 6b shows the inrush current waveform. the cur- rent through c2 controls the gate voltage. at the end of the drain ramp, the gate voltage is charged to its final value. the gate-to-sense clamp limits the maxi- mum v gs to about 18v under any condition. board removal if the card is removed from a live backplane, the output capacitor on the card may not be immediately dis- charged. while the output capacitor is discharging, the max5948_ continues to operate as if the input supply were still connected because the output capacitor tem- porarily supplies operating current to the ic. if the cir- cuit is connected as in figure 7a, the voltage at the uv pin falls below the uvlo detect threshold, and the max5948_ turns off the external mosfet. if r4 in the circuit is connected directly to the -48v return, the external mosfet remains on until the capacitor is dis- charged sufficiently to drop the uv pin voltage to the uvlo detect threshold. in either case, when the mosfet is turned off, the out- put capacitor continues to discharge by the ic supply current i dd . the i dd flows into the ic at the v dd termi- nal, out at the v ee terminal, and back to the capacitor through the substrate diode of the external mosfet. there is also a parallel current path between the v ee and drain terminals through multiple internal esd-pro- tection diodes. the protection circuit built into the ic allows the drain terminal voltage to drop below that of logic and gate drive v cc and reference generator ref v cc ref v pg v ee 50mv v dd uv ov v ee sense gate drain pwrgd pwrgd max5948a MAX5948B output drive block diagram
max5948a/MAX5948B -48v hot-swap controllers with external r sense _______________________________________________________________________________________ 9 the v ee terminal so long as the absolute maximum allowed drain terminal current (-100ma) is not exceeded. as i dd is only 2ma maximum, this limiting current will not even be approached. electronic circuit breaker the max5948 provides a circuit-breaker feature that protects against excessive load current and short-cir- cuit conditions. the load current is monitored by sens- ing the voltage across an external sense resistor connected between v ee and sense. if the voltage between v ee and sense exceeds the current-limit trip voltage (v cb ) for a period of t phlsense , the electronic circuit breaker will trip, caus- ing the max5948a/MAX5948B to turn off the external mosfet as shown in figure 8. after an overcurrent fault condition, the circuit breaker can be reset by pulling the uv pin low and then pulling uv high or by cycling power to the max5948a/ MAX5948B. if more than 3? (typ) deglitch time (t phlsense ) is needed to prevent spurious shutdown due to load cur- rent spikes or noise, a simple lowpass filter can be used between the sense and v ee pins as shown in v ee sense gate drain v dd ov uv pwrgd MAX5948B -48v rtn -48v r4 562k ? 1% r5 9.09k ? 1% r6 10k ? 1% r1 0.02 ? 5% r3 18k ? 5% r2 10 ? 5% c1 150nf 25v q1 irf530 c2 3.3nf 100v gate in vicor vi-j3d-cy v in+ v in- c4 100 f 100v c3 0.1 f 100v * -48v rtn (short pin) *diodes inc. smat70a. figure 7a. inrush control circuitry gate - v ee 10v/div v ee 50v/div drain 50v/div inrush current 1a/div 4ms/div contact bounce figure 7b. input inrush current
max5948a/MAX5948B -48v hot-swap controllers with external r sense 10 ______________________________________________________________________________________ figure 9. resistor r7 and capacitor c3 slow down the response of the circuit breaker to filter momentary glitches in the sense voltage. the additional delay time can be estimated with the following equation: where i f is the current in fault condition, i i is the initial current before the fault, and i cb is the circuit-breaker trip current (i cb = v cb /r1). alternatively, the corre- sponding voltages across the sense resistor (v f , v i , and v cb ) may be used in the equation as shown. the sense pin of the max5948a/MAX5948B sources very little current (0.02? typ), so the addition of resistor r7 will introduce very little error in the circuit-breaker trip voltage. for example, a 10k ? resistor for r7 will only cause a 200? offset. example: a system has a 1a nominal load current and a 20m ? sense resistor. the circuit-breaker delay needs to be increased to 50? in response to a load current trcin vv vv rcin ii ii cbdly fi fcb fi fcb = ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? 73 73 gate - v ee 5v/div v ee 50v/div inrush current 2a/div 4ms/div contact bounce figure 8. startup into a short circuit v ee sense gate drain v dd ov uv pwrgd max5948a -48v rtn -48v r4 562k ? 1% r5 9.09k ? 1% r6 10k ? 1% r1 0.02 ? 5% r3 18k ? 5% r2 10 ? 5% c1 150nf 25v q1 irf530 c2 3.3nf 100v c4 100 f 100v * -48v rtn (short pin) *diodes inc. smat70a. c3 r7 figure 9. extending the short-circuit protection delay
max5948a/MAX5948B -48v hot-swap controllers with external r sense ______________________________________________________________________________________ 11 step to 5a. the circuit-breaker trip current is 50mv/20m ? = 2.5a. solving for r7 x c3 in the equation above yields a desired time constant of 100?. this can be achieved with r7 = 100 ? and c3 = 1?. in the event of a short circuit at the output, the input supply may dip below the uv threshold, resetting the circuit breaker. the max5948 cycles on and off until the short is removed, which can be minimized by creat- ing a deglitching delay at the uv pin with a capacitor from uv to v ee . this allows the input supply to recover before the uv pin resets the circuit breaker. figure 10 shows a circuit that automatically resets the circuit breaker after a current fault. transistors q2 and q3 along with c4, d1, r7, and r8 form a programma- ble one-shot circuit. in normal operation, the gate pin is pulled high and q3 is turned on, pulling node 2 to v ee . resistor r8 turns off q2. when a short occurs, the gate pin is pulled low and q3 turns off. node 2 starts to charge c4 and q2 turns on, pulling the uv pin low and resetting the circuit breaker. the instant c4 is fully charged, r8 turns off q2, uv goes high and the gate starts to ramp up. q3 turns back on and pulls node 2 back to v ee . diode d1 clamps node 3 at one diode drop below v ee . the duty cycle is set to 10% to prevent q1 from overheating. undervoltage and overvoltage protection the uv and ov pins can be used to detect undervolt- age and overvoltage conditions. the uv and ov pins are internally connected to analog comparators with 20mv of hysteresis. when the uv voltage falls below its threshold or the ov voltage rises above its threshold, the gate pin is immediately pulled low. the gate pin is held low until uv goes high and ov is low indicating that the input supply voltage is within specification. v ee sense gate drain v dd ov uv pwrgd max5948a -48v rtn -48v rtn (short pin) * -48v *diodes inc. smat70a. r4 562k ? 1% r8 510k ? 5% r5 19.1k ? 1% r6 562k ? 1% r7 1m ? 5% r9 10k ? 1% r1 0.02 ? 5% r3 18k ? 5% r2 10 ? 5% c1 150nf 25v c4 1 f 100v q1 irf530 d1 1n4148 q2 2n2222 q3 zvn3310 c2 3.3nf 100v c3 100 f 100v gate 2v/div node2 50v/div 1s/div node 2 figure 10. automatic restart after current fault
max5948a/MAX5948B the uv pin is also used to reset the circuit breaker after a fault condition has occurred. the uv pin can be pulled below v uvl to reset the circuit breaker. figure 11a shows how to program the undervoltage and overvoltage trip thresholds using three resistors. with r4 = 562k ? , r5 = 9.09k ? , and r6 = 10k ? , the undervoltage threshold is set to 37.2v (with a 37.8v release from undervoltage) and the overvoltage is set to 71.1v (with a 69.9v release from overvoltage). more hysteresis can be added to the undervoltage lockout with the circuit shown in figure 11b. resistor r3 connected between gate and uv lowers the sup- ply undervoltage lockout threshold (supply voltage decreasing) to: where v uvl is typically 1.223v. the supply voltage to release from undervoltage lockout (supply voltage increasing) is: where v uvh is typically 1.243v. the supply undervolt- age lockout hysteresis is the difference, or: where v uvhy is typically 20mv. vv rrrr rr rr v r r uv hys uvhy gate , = ++ ? ? ? ? ? ? + ? ? ? ? ? ? 231312 23 1 3 ? vv rrrr rr rr uv lh uvh , = ++ ? ? ? ? ? ? 231312 23 vv rrrr rr rr v r r uv hl uvl gate , = ++ ? ? ? ? ? ? ? ? ? ? ? ? ? 231312 23 1 3 ? -48v hot-swap controllers with external r sense 12 ______________________________________________________________________________________ v ee v dd ov uv max5948a MAX5948B -48v rtn -48v v uv = 1.223 r4 + r5 + r6 r5 + r6 r4 r5 r6 -48v rtn (short pin) v ov = 1.223 r4 + r5 + r6 r6 figure 11a. undervoltage and overvoltage sensing v ee sense gate v dd uv ov max5948 -48v rtn = 37.6v uv -48v rtn (short pin) * -48v *diodes inc. smat70a. r1 562k ? 1% r4 506k ? 1% r2 16.9k ? 1% r5 8.87k ? 1% r7 0.02 ? 5% r6 10 ? 5% c1 150nf 25v q1 irf530 r3 1.62m ? 1% = 43v uv = 71v ov figure 11b. programmable hysteresis for undervoltage
a separate resistor-divider must be used for the over- voltage lockout setting. the supply overvoltage lockout threshold is: where v ovh is typically 1.223v. using r1 = 562k ? , r2 = 16.9k ? , r3 = 1.62m ? , r4 = 506k ? , r5 = 8.87k ? , and the typical value of v gate = 13.5v results in the following thresholds: v uv,hl = 37.6v v uv,lh = 43v (with hysteresis now increased to 5.4v), and v ov = 71v (with 1.2v hysteresis). pwrgd /pwrgd output the pwrgd (pwrgd) output can be used directly to enable a power module after hot insertion. the max5948a ( pwrgd ) can be used to enable modules with an active-low enable input (figure 13), while the MAX5948B (pwrgd) is used to enable modules with an active-high enable input (figure 12). the pwrgd signal is referenced to the drain termi- nal, which is the negative supply of the power module. the pwrgd signal is referenced to v ee . when the drain voltage of the max5948a is high with respect to v ee , the internal pulldown mosfet q2 is off and the pwrgd pin is in a high-impedance state (figure 13). pwrgd is pulled high by the module? internal pullup current source, turning the module off. when the drain voltage drops below v pg , q2 turns on and pwrgd pulls low, enabling the module. the pwrgd signal can also be used to turn on an led or optoisolator to indicate that the power is good (figure 13) (see the component selection procedure section). vv rr r ov ovh = + ? ? ? ? ? ? 45 5 max5948a/MAX5948B -48v hot-swap controllers with external r sense ______________________________________________________________________________________ 13 pwrgd i1 v ee v pg -48v r1 r2 c1 q1 r3 c2 MAX5948B v in+ v in- c4 q2 q3 v out+ v out- on/off vicor vi-j3d-cy drain gate sense v ee v dd r4 r5 r6 * *diodes inc. smat70a. -48v rtn -48v rtn (short pin) uv ov figure 12. active-high enable module
max5948a/MAX5948B when the drain voltage of the MAX5948B is high with respect to v ee (figure 12), the internal mosfet q3 is turned off so that i1 and the internal mosfet q2 clamp the pwrgd pin to the drain pin. mosfet q2 sinks the module? pullup current, and the module turns off. when the drain voltage drops below v pg , mosfet q3 turns on, shorting i1 to v ee and turning q2 off. the pullup current in the module pulls pwrgd high, enabling the module. gate voltage regulation gate goes high when the following startup conditions are met: uv is high, ov is low, the supply voltage is above v uv,lh , and (v sense - v ee ) is less than 50mv. gate is pulled up with a 45? current source and is regulated at 13.5v above v ee . the max5948a/ MAX5948B include an internal clamp that ensures the gate voltage of the external mosfet never exceeds 18v. during a fast-rising v dd , the clamp also keeps the gate and sense potentials as close as possible to prevent the fet from accidentally turning on. when a fault condition is detected, gate is pulled low with a 50ma current. drain pin protection the max5948? drain pin withstands negative volt- ages (referenced to v ee ); no external diode is required. when the -48v backplane shorts to ground and v ee becomes 0v, the drain pin is held at less than 1.5v (sum of q1? body diode and voltage drop across r1) below v ee due to the storage capacitor c3 (figure 13). the -1.5v results in a 50ma reverse drain current, which is within the capability of the max5948. a design with r1 larger than 0.1 ? may require a resistor in series with the drain pin to avoid exceeding the 50ma drain current maximum. -48v hot-swap controllers with external r sense 14 ______________________________________________________________________________________ pwrgd v ee v pg -48v r1 r2 c1 q1 r3 c2 max5948a v in+ v in- c4 v out+ v out- on/off active-high enable module drain gate sense v ee v dd r4 r5 r6 * *diodes inc. smat70a. -48v rtn -48v rtn (short pin) uv ov q2 figure 13. active-low enable module
applications information (refer to the typical operating circuit. ) sense resistor the circuit-breaker threshold is set to 50mv (typically). select a sense resistor that causes a drop equal to or above the current-limit threshold at a current level above the maximum normal operating current. typically, set the overload current to 1.5 to 2.0 times the nominal load cur- rent plus the load-capacitance charging current during startup. choose the sense resistor power rating to be greater than (v cb ) 2 / r sense . component selection procedure determine load capacitance: c l = c3 + c4 + module input capacitance determine load current, i load . select circuit-breaker current, for example: i cb = 2 x i load ?al culate r sense : realize that i cb varies ?0% due to trip-voltage tolerance. set allowable inrush current: determine value of c2: calculate value of c1: cccx vv v gd in max gs th gs th 12 =+ ? ? ? ? ? ? ? () () () () c axc i l inrush 2 45 = ix mv r ior ii xi inrush sense load inrush load cb min ? + 08 40 08 . . () r mv i sense cb = 50 max5948a/MAX5948B -48v hot-swap controllers with external r sense ______________________________________________________________________________________ 15 v ee sense gate drain v dd ov uv pwrgd max5948a gnd (short pin) -48v r4 562k ? 1% r5 9.09k ? 1% r6 10k ? 1% r1 0.02 ? 5% r3 18k ? 5% r2 10 ? 5% c1 150nf 25v q1 irf530 c2 3.3nf 100v c3 100 f 100v * gnd *diodes inc. smat70a. moc207 r7 51k ? 5% pwrgd figure 14. using pwrgd to drive an optoisolator
max5948a/MAX5948B -48v hot-swap controllers with external r sense 16 ______________________________________________________________________________________ v ee sense gate drain v dd ov 5v uv pwrgd max5948a gnd (short pin) -48v r4 562k ? 1% r5 9.09k ? 1% r6 10k ? 1% r1 0.02 ? 5% r3 18k ? 5% r2 10 ? 5% c1 150nf 25v q1 irf530 c2 3.3nf 100v sense- sense+ trim on/off lucent jw050a1-e v in+ v in- v out+ v out- c4 100 f 100v c5 100 f 16v c3 0.1 f 100v * gnd *diodes inc. smat70a. t ypical operating circuit determine value of r3: set r2 = 10 ? . if an optocoupler is utilized as in figure 14, deter- mine the led series resistor: although the suggested optocoupler is not specified for operation below 5ma, its performance is adequate for 36v temporary low-line voltage where led current would then be 2.2ma to 3.7ma. if r7 is set as high as 51k ? , optocoupler operation should be verified over the expected temperature and input voltage range to ensure suitable operation when led current 0.9ma for 48v input and 0.7ma for 36v input. if input transients are expected to momentarily raise the input voltage to >100v, select an input transient-volt- age-suppression diode (tvs) to limit maximum voltage on the max5948 to less than 100v. a suitable device is the diodes inc. smat70a telecom-specific tvs. select q1 to meet supply voltage, load current, efficien- cy, and q1 package power-dissipation requirements: bv dss 100v i d(on) 3x i load dpak, d 2 pak, or to-220ab choose the lowest practical r ds(on) within budget constraints. mosfets with values from 14m ? to 540m ? are available at 100v breakdown. ensure that the temperature rise of q1 junction is not excessive at normal load current for the package select- ed. ensure that i cb current during voltage transients does not exceed allowable transient-safe operating-area limitations. this is determined from the soa and tran- sient-thermal-resistance curves in the q1 manufacturer? data sheet. example 1: i load = 2.5a, efficiency = 98%, then v ds = 0.96v is acceptable, or r ds(on) 384m ? at operating temper- ature is acceptable. an irl520ns 100v nmos with r ds(on) 180m ? and i d(on) = 10a is available in d 2 pak. (a vishay siliconix sud40n10-25 100v nmos with r ds(on) 25m ? and i d(on) = 40a is available in dpak, but may be more costly because of a larger die size). r vv ma i ma in nominal led 7 2 35 () = ? ? r s c 3 2 150
using the irl520ns, v ds 0.625v even at +80? so efficiency 98.6% at 80?. p d 1.56w and junction temperature rise above case temperature would be 5? due to the package jc = 3.1?/w thermal resistance. of course, using the sud40n10-25 would yield an effi- ciency greater than 99.8% to compensate for the increased cost. if i cb is set to twice i load , or 5a, v ds momentarily dou- bles to 1.25v. if c out = 4000?, transient-line input voltage is ? 36v, the 5a charging-current pulse is: entering the data sheet transient-thermal-resistance curves at 1ms provides a jc = 0.9?/w. p d = 6.25w, so ? t jc = 5.6?. clearly, this is not a problem. example 2: i load = 10a, efficiency = 98%, allowing v ds = 0.96v but r ds(on) 96m ? . an irf530 in a d 2 pak exhibits r ds(on) 90m ? at +25? and 135m ? at +80?. power dissipation is 9.6w at +25? or 14.4w at +80?. junction-to-case thermal resistance is 1.9w/?, so the junction temperature rise would be approximately 5c above the +25? case temperature. for higher efficien- cy, consider irl540ns with r ds(on) 44m ? . this allows = 99%, p d 4.4w, and t jc = +4? ( jc = 1.1?/w) at +25?. thermal calculations for the transient condition yield i cb = 20a, v ds = 1.8v, t = 0.5ms, transient jc = 0.12?/w, p d = 36w and ? t jc = 4.3?. t fx v a ms == 4000 1 25 5 1 . max5948a/MAX5948B -48v hot-swap controllers with external r sense ______________________________________________________________________________________ 17 chip information transistor count: 2645 process: bicmos
max5948a/max5984b -48v hot-swap controllers with external r sense maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 18 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) soicn .eps package outline, .150" soic 1 1 21-0041 b rev. document control no. approval proprietary information title: top view front view max 0.010 0.069 0.019 0.157 0.010 inches 0.150 0.007 e c dim 0.014 0.004 b a1 min 0.053 a 0.19 3.80 4.00 0.25 millimeters 0.10 0.35 1.35 min 0.49 0.25 max 1.75 0.050 0.016 l 0.40 1.27 0.394 0.386 d d min dim d inches max 9.80 10.00 millimeters min max 16 ac 0.337 0.344 ab 8.75 8.55 14 0.189 0.197 aa 5.00 4.80 8 n ms012 n side view h 0.244 0.228 5.80 6.20 e 0.050 bsc 1.27 bsc c h e e b a1 a d 0 -8 l 1 variations:

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